The present invention relates to a nonvolatile memory of a field effect transistor (FET).
FIG. 5 shows a conventional nonvolatile memory having a MNOS structure. An oxide layer 4 of SiO.sub.2 and a nitride layer 5 of SiN are sequentially formed on a channel between a source region 2 and a drain region 3 of a semiconductor substrate 1, and constitute an insulating layer interposed between the substrate 1 and a gate electrode 6. At the time of writing an electric charge, a high voltage E1 is applied between the substrate 1 and the gate electrode 6 to thereby allow electrons to tunnel through the oxide layer 4 from the substrate side into the nitrile layer 5, where they are trapped. At the time of reading out the electric charge, a low voltage E2 is applied to provide such a state that a current can flow between the source region 2 and the drain region 3 (the FET is turned on). Of course, if the high voltage El was not applied during the writing, there exist no electrons trapped in the nitride layer 5, providing such a state in the reading that no current can flow between the source region 2 and the drain region 3 (i.e., the FET is turned off).
In order to erase the above trapping state of electrons, a high voltage E3 of the opposite polarity is applied to have the electrons return to the substrate side.
As described above, in the conventional nonvolatile memory, an electric charge is injected into and removed from the nitride layer 5 through the oxide layer 4. Therefore, the oxide layer 4 deteriorates in quality. The deterioration of the layer quality makes it easier for the electric charge to flow therethrough (i.e., to escape from the nitride layer 5), which worsens the data storing performance of the memory. Further, while the oxide layer 4 must have a small thickness of 15-30 .ANG. to allow an electric charge to go through it, it is generally difficult to form such a thin oxide layer uniformly in a stable manner.
On the other hand, the thickness of the nitride layer 5 of SiN is determined in view of the trapping length of a hole, and it is known that if the thickness of the nitride layer 5 is 190 .ANG. or less, the memory performance is degraded. That is, the nitride layer 5 should have a thickness of more than 190 .ANG.. However, with such a thick nitride layer, a higher voltage develops across the nitride layer 5 during the writing and erasing. This causes a problem that the amount of energy consumed in the nitride layer 5 is greater than that required for the writing or erasing itself of data.